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This guide will explain how to setup an EDK 12.1 project to interface with two 16-bit Atmel (AT49BV322D, AT49BV322DT, AT49BV322A, AT49BV322AT) Flash Memory parts organized in parallel acting as a single 32-bit Flash Memory using the Xilinx XPS_MCH_EMC IP Core.<br />
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Tweaking of the XPS_MCH_EMC Properties is necessary because this Flash Configuration is addressed like a 16-bit Flash but data is read & written like a 32-bit Flash. By default, the XPS_MCH_EMC is not setup to handle this situation. The XPS_MCH_EMC is designed not to allow a user to write to a none word width boundary. That is to say, each address location specifies 8 bits of data. Each time the lowest bit of the address is incremented the internal Flash pointer shifts ahead by 8 bits. If we use an 8-bit word the XPS_MCH_EMC lets us write to any location. If we use a 16-bit word we can write to every other address location (we cannot write a 1 to the bottom most bit). If we use a 32-bit word we can write to every 4th address location (we cannot write a 1 to the bottom 2 bits). Here in lies the problem because our Flash architecture (using 2 16-bit Flash parts with their data bits in parallel) is addressed like a 16-bit data word but is, in fact, a 32-bit data word. We must trick the XPS_MCH_EMC into thinking we are using a 32-bit data word. This crux of the solution is to ignore the least 2 significant bits of the Address. This is possible because the XPS_MCH_EMC supports a 32-bit address but we only need 21 bits of address. When we shift left by 2 we align any address we write onto a 32-bit boundary. We then, simply, ignore the bottom 2 bits.<br />
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Though this guide has been written from experimentation with EDK 12.1, the procedures should be extremely similar to for earlier version of EDK.<br />
