How to add VHDL files to a WILDSTAR4 project

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This guide tells what steps need to be taken to add additional VHDL files to the WILDSTAR4 build process. You would need to do this if, for instance, you have written a state machine component in VHDL that you wish to instantiate within your top level PE design.


1.) Navigate to your synthesis/<pe>/xst directory and open <project name>.prj. Add the the appropriate lines to the top of the file. The order here matters. VHDL with be referenced top to bottom. So if file A references VHDL in file B, file A must be below file B on the list.

     EXAMPLES

    vhdl WILDSTAR4_LIBRARY ../../../simulation/RF_gadget.vhd

    vhdl WILDSTAR4_LIBRARY C:/widgets/VHDL/fifo/fifo8x512.vhd


2.) To include Xilinx primitives, ensure that the follow lines are the top of the primitive-calling file. These 2 lines should *NOT* be surrounded by "-- synopsys translate_off" & "--synopsys translate_on"

     Library UNISIM;
     use UNISIM.Vcomponents.all;



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