Changes

1.) Navigate to your synthesis/<pe>/xst directory and open <project name>.prj. Add the the appropriate lines to the top of the file. The order here matters. VHDL with be referenced top to bottom. So if file A references VHDL in file B, file A must be below file B on the list.<br /><br />

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EXAMPLES<br />

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2.) To include Xilinx primitives, ensure that the follow lines are the top of the primitive-calling file. These 2 lines should *NOT* be surrounded by "-- synopsys translate_off" & "--synopsys translate_on"<br />

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[[Category:WILDSTAR4]] [[Category:VHDL]]